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CY28409
Clock Synthesizer with Differential SRC and CPU Outputs
Features
* Supports Intel Pentium 4-type CPUs * Selectable CPU frequencies * 3.3V power supply * Ten copies of PCI clocks * Five copies of 3V66 with one optional VCH * Two copies 48 MHz USB clocks
CPU x3 SRC x1 3V66 x5 PCI x 10 REF x2 48M x2
* Three differential CPU clock pairs * One differential SRC clock * I2C support with readback capabilities * Ideal Lexmark Spread Spectrum profile for maximum EMI reduction * 56-pin SSOP and TSSOP packages
Block Diagram
XIN XOUT CPU_STP# PCI_STP# FS_[A:B] VTT_PWRGD# IREF VDD_3V66 3V66_[0:3]
Pin Configuration
VDD_REF REF0:1
[1]
XTAL OSC PLL1 ~
PLL Ref Freq
Divider Network VDD_CPU CPUT[0:2], CPUC[0:2] VDD_SRC SRCT, SRCC
PLL2
2
VDD_PCI PCIF[0:2] PCI[0:6]
3V66_4/VCH VDD_48MHz DOT_48 USB_48
PD#
SDATA SCLK
I2C Logic
REF_0 REF_1 VDD_REF XIN XOUT VSS_REF PCIF0 PCIF1 PCIF2 VDD_PCI VSS_PCI PCI0 PCI1 PCI2 PCI3 VDD_PCI VSS_PCI PCI4 PCI5 PCI6 PD# 3V66_0 3V66_1 VDD_3V66 VSS_3V66 3V66_2 3V66_3 SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
FS_B VDD_A VSS_A VSS_IREF IREF FS_A CPU_STP# PCI_STP# VDD_CPU CPUT2 CPUC2 VSS_CPU CPUT1 CPUC1 VDD_CPU CPUT0 CPUC0 VSS_SRC SRCT SRCC VDD_SRC VTT_PWRGD# VDD_48 VSS_48 DOT_48 USB_48 SDATA 3V66_4/VCH
56 SSOP/TSSOP
CY28409
Note: 1. Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.
Rev 1.0, November 22, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 16
www.SpectraLinear.com
CY28409
Pin Description
Pin No. 1, 2 4 XIN Name REF(0:1) Type I Description Crystal Connection or External Reference Frequency Input. This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. O, SE Reference Clock. 3.3V 14.318-MHz clock output.
5 41,44,47 40,43,46 38, 37 22,23,26,27 29 7,8,9 12,13,14, 15,18,19,20 31, 32 51,56 52 21 50 49 35 30 28 53 55 54 42,48 45 36 39 34 33 10,16 11,17 24 25 3 6
XOUT CPUT(0:2) CPUC(0:2) SRCT, SRCC 3V66(0:3) 3V66_4VCH PCIF(0:2) PCI(0:6) USB_48 DOT_48 FS_A, FS_B IREF PD# CPU_STP# PCI_STP# VTT_PWRGD# SDATA SCLK VSS_IREF VDD_A VSS_A VDD_CPU VSS_CPU VDD_SRC VSS_SRC VDD_48 VSS_48 VDD_PCI VSS_PCI VDD_3V66 VSS_3V66 VDD_REF VSS_REF
O, SE Crystal Connection. Connection for an external 14.318-MHz crystal output. O, DIF CPU Clock Output. Differential CPU clock outputs. See Table 1 for frequency configuration. O, DIF CPU Clock Output. Differential CPU clock outputs. See Table 1 for frequency configuration. O, DIF Differential serial reference clock. O, SE 66-MHz Clock Output. 3.3V 66-MHz clock from internal VCO. O, SE 48-/66-MHz Clock Output. 3.3V selectable through SMBus to be 66 or 48 MHz. O, SE Free-running PCI Output. 33-MHz clocks divided down from 3V66. O, SE PCI Clock Output. 33-MHz clocks divided down from 3V66. O, SE Fixed 48-MHz clock output. O, SE Fixed 48-MHz clock output. I I I, PU I, PU I, PU I I/O I GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND 3.3V LVTTL input for CPU frequency selection. Current Reference. A precision resistor is attached to this pin which is connected to the internal current reference. 3.3V LVTTL input for Power-Down# active LOW. 3.3V LVTTL input for CPU_STP# active LOW. 3.3V LVTTL input for PCI_STP# active LOW. 3.3V LVTTL input is a level sensitive strobe used to latch the FS_A and FS_B inputs (active LOW). SMBus-compatible SDATA. SMBus-compatible SCLOCK. Ground for current reference. 3.3V power supply for PLL. Ground for PLL. 3.3V power supply for outputs. Ground for outputs. 3.3V power supply for outputs. Ground for outputs. 3.3V power supply for outputs. Ground for outputs. 3.3V power supply for outputs. Ground for outputs. 3.3V power supply for outputs. Ground for outputs. 3.3V power supply for outputs. Ground for outputs.
Rev 1.0, November 22, 2006
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CY28409
Table 1. Frequency Select Table (FS_A, FS_B) FS_A 0 0 0 1 1 FS_B 0 MID 1 0 MID CPU 100 MHz REF/N 200 MHz 133 MHz Hi-Z SRC 100/200 MHz REF/N 100/200 MHz 100/200 MHz Hi-Z 3V66 66 MHz REF/N 66 MHz 66 MHz Hi-Z PCIF/PCI 33 MHz REF/N 33 MHz 33 MHz Hi-Z REF0 14.3 MHz REF/N 14.3 MHz 14.3 MHz Hi-Z REF1 14.31 MHz REF/N 14.31 MHz 14.31 MHz Hi-Z USB/DOT 48 MHz REF/N 48 MHz 48 MHz Hi-Z
Table 2. Frequency Select Table (FS_A, FS_B) SMBus Bit 5 of Byte 6 = 1 FS_A 0 0 1 FS_B 0 1 0 CPU 200 MHz 400 MHz 266 MHz SRC 100/200 MHz 100/200 MHz 100/200 MHz 3V66 66 MHz 66 MHz 66 MHz PCIF/PCI 33 MHz 33 MHz 33 MHz REF0 14.3 MHz 14.3 MHz 14.3 MHz REF1 14.31 MHz 14.31 MHz 14.31 MHz USB/DOT 48 MHz 48 MHz 48 MHz
Frequency Select Pins (FS_A, FS_B)
Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A and FS_B inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled LOW by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A and FS_B input values. For all logic levels of FS_A and FS_B except MID, VTT_PWRGD# employs a one-shot functionality in that once a valid LOW on VTT_PWRGD# has been sampled LOW, all further VTT_PWRGD#, FS_A and FS_B transitions will be ignored. In the case where FS_B is at mid level when VTT_PWRGD# is sampled LOW, the clock chip will assume "Test Clock Mode." Once "Test Clock Mode" has been invoked, all further FS_B transitions will be ignored and FS_A will asynchronously select between the Hi-Z and REF/N mode. Exiting test mode is accomplished by cycling power with FS_B in a HIGH or LOW state.
Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3. The block write and block read protocol is outlined in Table 4 while Table 5 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Table 3. Command Code Definition Bit 7 (6:0)
Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 4. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Description Bit 1 2:8 9 10 11:18 19 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Block Read Protocol Description
Rev 1.0, November 22, 2006
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CY28409
Table 4. Block Read and Block Write Protocol (continued) Block Write Protocol Bit 20:27 28 29:36 37 38:45 46 .... .... .... .... .... .... Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave ...................... Data Byte (N-1) - 8 bits Acknowledge from slave Data Byte N - 8 bits Acknowledge from slave Stop Description Bit 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... Table 5. Byte Read and Byte Write protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '100xxxxx' stands for byte operation, bits[4:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '100xxxxx' stands for byte operation, bits[4:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Data byte from slave - 8 bits Acknowledge from master Stop Byte Read Protocol Description Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte count from slave - 8 bits Acknowledge from master Data byte from slave - 8 bits Acknowledge from master Data byte from slave - 8 bits Acknowledge from master Data byte N from slave - 8 bits Acknowledge from master Stop Block Read Protocol Description
19 20:27 28 29
19 20 21:27 28 29 30:37 38 39
Control Registers
Byte 0:Control Register 0 Bit 7 6 @Pup 0 1 Reserved PCIF PCI Reserved Reserved Name Reserved, Set = 0 PCI Drive Strength Override 0 = Force All PCI and PCIF Outputs to Low Drive Strength 1 = Force All PCI and PCIF Outputs to High Drive Strength Reserved, Set = 0 Reserved, Set = 0 Description
5 4
0 0
Rev 1.0, November 22, 2006
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CY28409
Byte 0:Control Register 0 (continued) Bit 3 2 1 0 @Pup Externally Selected Externally Selected Externally Selected Externally Selected Name PCI_STP# CPU_STP# FS_B FS_A Description PCI_STP# reflects the current value of the external PCI_STP# pin. 0 = PCI_STP# pin is LOW. CPU_STP# reflects the current value of the external CPU_STP# pin. 0 = CPU_STP# pin is LOW. FS_B reflects the value of the FS_B pin sampled on power-up. FS_A reflects the value of the FS_A pin sampled on power-up.
Byte 1: Control Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 0 1 1 1 1 1 1 1 Name SRCT, SRCC SRCT, SRCC Reserved Reserved Reserved CPUT2, CPUC2 CPUT1, CPUC1 CPUT0, CPUC0 Description Allows control of SRCT/C with assertion of PCI_STP# or SW PCI_STP 0 = Free Running, 1 = Stopped with PCI_STP# SRCT/C Output Enable; 0 = Disabled (Hi-z), 1 = Enabled Reserved, Set = 1 Reserved, Set = 1 Reserved, Set = 1 CPUT/C2 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled CPUT/C1 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled CPUT/C0 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
Byte 2: Control Register 2 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name SRCT, SRCC SRCT, SRCC CPUT2, CPUC2 CPUT1, CPUC1 CPUT0, CPUC0 CPUT2, CPUC2 CPUT1, CPUC1 CPUT0, CPUC0 Description SRCT/C Pwrdwn Drive Mode 0 = Driven during power-down, 1 = Three-state during power-down SRCT/C Stop Drive Mode 0 = Driven during PCI_STP, 1 = Three-state during PCI_STP CPUT/C2 Pwrdwn Drive Mode 0 = Driven during power-down, 1 = Three-state during power-down CPUT/C1 Pwrdwn Drive Mode 0 = Driven during power-down, 1 = Three-state during power-down CPUT/C0 Pwrdwn Drive Mode 0 = Driven during power-down, 1 = Three-state during power-down CPUT/C2 stop Drive Mode 0 = Driven when stopped, 1 = Three-state when stopped CPUT/C1 stop Drive Mode 0 = Driven when stopped, 1 = Three-state when stopped CPUT/C0 stop Drive Mode 0 = Driven when stopped, 1 = Three-state when stopped
Byte 3: Control Register 3 Bit 7 @Pup 1 Name SW PCI STOP Description SW PCI_STP Function 0= PCI_STP assert, 1= PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will resume in a synchronous manner with no short pulses. PCI6 Output Enable 0 = Disabled, 1 = Enabled
6
1
PCI6
Rev 1.0, November 22, 2006
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CY28409
Byte 3: Control Register 3 (continued) Bit 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Name PCI5 Output Enable 0 = Disabled, 1 = Enabled PCI4 Output Enable 0 = Disabled, 1 = Enabled PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled PCI1 Output Enable 0 = Disabled, 1 = Enabled PCI0 Output Enable 0 = Disabled, 1 = Enabled Description
Byte 4: Control Register 4 Bit 7 6 5 4 3 2 1 0 @Pup 0 1 0 0 0 1 1 1 USB_48 USB_48 PCIF2 PCIF1 PCIF0 PCIF2 PCIF1 PCIF0 Name Description USB_48 Drive Strength 0 = High drive strength, 1 = Low drive strength USB_48 Output Enable 0 = Disabled, 1 = Enabled Allow control of PCIF2 with assertion of PCI_STP# or SW PCI_STP 0 = Free Running, 1 = Stopped with PCI_STP# Allow control of PCIF1 with assertion of PCI_STP# or SW PCI_STP 0 = Free Running, 1 = Stopped with PCI_STP# Allow control of PCIF0 with assertion of PCI_STP# or SW PCI_STP 0 = Free Running, 1 = Stopped with PCI_STP# PCIF2 Output Enable 0 = Disabled, 1 = Enabled PCIF1 Output Enable 0 = Disabled, 1 = Enabled PCIF0 Output Enable 0 = Disabled, 1 = Enabled
Byte 5: Control Register 5 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 0 1 1 1 1 1 DOT_48 Reserved 3V66_4/VCH 3V66_4/VCH 3V66_3 3V66_2 3V66_1 3V66_0 Name DOT_48 Output Enable 0 = Disabled, 1 = Enabled Reserved, Set = 1 VCH Select 66-MHz/48-MHz 0 = 3V66 mode, 1 = VCH (48-MHz) mode 3V66_4/VCH Output Enable 0 = Disabled, 1 = Enabled 3V66_3 Output Enable 0 = Disabled, 1 = Enabled 3V66_2 Output Enable 0 = Disabled, 1 = Enabled 3V66_1 Output Enable 0 = Disabled, 1 = Enabled 3V66_0 Output Enable 0 = Disabled, 1 = Enabled Description
Rev 1.0, November 22, 2006
Page 6 of 16
CY28409
Byte 6: Control Register 6 Bit 7 6 5 @Pup 0 0 0 Reserved Reserved CPUC0, CPUT0 CPUC1, CPUT1 CPUC2, CPUT2 SRCT, SRCC Reserved PCIF PCI 3V66 SRCT,SRCC CPUT_ITP,CPUC_ITP REF_1 REF_0 Name Reserved, Set = 0 Reserved, Set = 0 FS_A & FS_B Operation 0 = Normal, 1 = Test mode SRC Frequency Select 0 = 100 MHz, 1 = 200 MHz Reserved, Set = 0 Spread Spectrum Enable 0 = Spread Off, 1 = Spread On Description
4 3 2
0 0 0
1 0
1 1
REF_1 Output Enable 0 = Disabled, 1 = Enabled REF_0 Output Enable 0 = Disabled, 1 = Enabled
Byte 7: Vendor ID Bit 7 6 5 4 3 2 1 0 @Pup 0 1 0 0 1 0 0 0 Name Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description
Table 6. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 50 ppm Stability (max.) 50 ppm Aging (max.) 5 ppm
Crystal Recommendations
The CY28409 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28409 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading.
Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It's a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL).
Figure 1. Crystal Capacitive Clarification
Rev 1.0, November 22, 2006
Page 7 of 16
CY28409
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides.
C lo c k C h ip (C Y 2 8 4 0 9 ) C i1 C i2 P in 3 to 6 p
Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL - (Cs + Ci) Total Capacitance (as seen by the crystal) 1 CLe = 1 1 ( Ce1 + Cs1 + Ci1 + Ce2 + Cs2 + Ci2 ) CL....................................................Crystal load capacitance CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Cs .............................................. Stray capacitance (terraced) Ci ...........................................................Internal capacitance (lead frame, bond wires etc.) PD# (Power-down) Clarification
C s1
X1
X2
C s2 T ra c e 2 .8 p F
XTAL Ce1
C e2
T r im 33pF
Figure 2. Crystal Loading Example
The PD# (Power-down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is LOW, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so as not to cause glitches while changing to the low `stopped' state. PD# Assertion When PD# is sampled LOW by two consecutive rising edges of the CPUC clock then all clock outputs (except CPU) clocks must be held LOW on their next HIGH-to-LOW transition. CPU clocks must be held with CPU clock pin driven HIGH with a value of 2 x Iref and CPUC undriven. Due to the state of internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete
PD# CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF
Figure 3. Power-down Assertion Timing Waveform
Rev 1.0, November 22, 2006
Page 8 of 16
CY28409
PD# Deassertion The power-up latency between PD# rising to a valid logic `1' level and the starting of all clocks is less than 1.8 ms. CPU_STP# Assertion The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped after being sampled by two rising edges of the internal CPUT clock. The final states of the stopped CPU signals are CPUT = HIGH and CPUC = LOW.
Tstable <1.8 ms
There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal to (Mult 0 `select') x (Iref), and the CPUC signal will not be driven. Due to the external pull-down circuitry, CPUC will be LOW during this stopped state. CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles.
PD# CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF
Tdrive_PWRDN# <300 s, >200 mV
Figure 4. Power-down Deassertion Timing Waveform
CPU_STP#
CPUT CPUC
Figure 5. CPU_STP# Assertion Waveform
CPU_STP# CPUT CPUC
CPU Internal
Tdrive_CPU_STP#, 10 ns > 200 mV
Figure 6. CPU_STP# Deassertion Waveform
Rev 1.0, November 22, 2006
Page 9 of 16
CY28409
PCI_STP# Assertion[2] The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tSU). (See Figure 7.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free-running.
Tsu
PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a high level.
PCI_STP# PCI_F
PCI SRC 100MHz
Figure 7. PCI_STP# Assertion Waveform
Tsu Tdrive_SRC
PCI_STP# PCI_F
PCI SRC 100MHz
Figure 8. PCI_STP# Deassertion Waveform
Note: 2. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These two inputs are logically ANDed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the device's stoppable PCI clocks are not running.
Rev 1.0, November 22, 2006
Page 10 of 16
CY28409
FS_A, FS_B VTT_PWRGD# PWRGD_VRM
VDD Clock Gen Clock State State 0
0.2-0.3 ms Delay State 1
Wait for VTT_PWRGD#
Sample Sels State 2 State 3
Device is not affected, VTT_PWRGD# is ignored
Clock Outputs
Off
On
Clock VCO
Off
On
Figure 9. VTT_PWRGD# Timing Diagram
S1
S2 VTT_PWRGD# = Low
Delay >0.25 ms
VDDA = 2.0V
Sample Inputs straps
Wait for <1.8 ms S0 S3 VDDA = off
Power Off
Normal Operation
VTT_PWRGD# = toggle
Enable Outputs
Figure 10. Clock Generator Power-up/Run State Diagram
Rev 1.0, November 22, 2006
Page 11 of 16
CY28409
Absolute Maximum Conditions
Parameter VDD VDD_A VIN TS TA TJ OJC OJA ESDHBM UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Condition Min. -0.5 -0.5 -0.5 -65 0 - - - 2000 Max. 4.6 4.6 VDD + 0.5 150 70 150 15 45 - V-0 1 Unit V V VDC C C C C/W C/W V
Relative to VSS Non-functional Functional Functional Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) MIL-STD-883, Method 3015 @ 1/8 in.
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter VDD_A, VDD_REF, VDD_PCI, VDD_3V66, VDD_48, VDD_CPU VILI2C VIHI2C VIL VIH IIL IIH VOL VOH IOZ IDD CIN COUT LIN VXIH VXIL IPD3.3V Description 3.3V Operating Voltage Condition 3.3 5% Min. 3.135 Max. 3.465 Unit V
Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Leakage Current Input High Leakage Current Output Low Voltage Output High Voltage High-impedance Output Current Dynamic Supply Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Xin High Voltage Xin Low Voltage Power-down Supply Current
- 1.0 2.2 - VSS - 0.5 0.8 2.0 VDD + 0.5 except internal pull-ups resistors, 0 < VIN < VDD -5 except internal pull-down resistors, 0 < VIN < VDD 5 IOL = 1 mA - 0.4 IOH = -1 mA 2.4 - -10 10 All outputs loaded per Table 9 and Figure 11 - 350 2 5 3 6 - 7 0.7VDD VDD 0 0.3VDD PD# Asserted - 1
SDATA, SCLK SDATA, SCLK
V V V V A A V V A mA pF pF nH V V mA
AC Electrical Specifications
Parameter Description Crystal TDC XIN Duty Cycle Condition The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When XIN is driven from an external clock source Measured between 0.3VDD and 0.7VDD As an average over 1- s duration Over 150 ms Min. 47.5 Max. 52.5 Unit %
TPERIOD T R / TF TCCJ LACC
XIN Period XIN Rise and Fall Times XIN Cycle to Cycle Jitter Long-term Accuracy
69.841 - -
71.0 10.0 500 300
ns ns ps ppm
Rev 1.0, November 22, 2006
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CY28409
AC Electrical Specifications (continued)
Parameter Description CPU at 0.7V TDC CPUT and CPUC Duty Cycle 100-MHz CPUT and CPUC Period TPERIOD TPERIOD 133-MHz CPUT and CPUC Period 200-MHz CPUT and CPUC Period TPERIOD Any CPUT/C to CPUT/C Clock Skew TSKEW TCCJ CPUT/C Cycle to Cycle Jitter CPUT and CPUC Rise and Fall Times T R / TF Rise/Fall Matching TRFM TR Rise Time Variation Fall Time Variation TF Voltage High VHIGH VLOW Voltage Low Crossing Point Voltage at 0.7V Swing VOX Maximum Overshoot Voltage VOVS Minimum Undershoot Voltage VUDS Ring Back Voltage VRB SRC TDC SRCT and SRCC Duty Cycle 100 MHz SRCT and SRCC Period TPERIOD TPERIOD 200 MHz SRCT and SRCC Period SRCT/C Cycle to Cycle Jitter TCCJ SRCT/C Long Term Accuracy LACC T R / TF SRCT and SRCC Rise and Fall Times Rise/Fall Matching TRFM Rise Time Variation TR TF Fall Time Variation Voltage High VHIGH Voltage Low VLOW VOX Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage VOVS Minimum Undershoot Voltage VUDS Ring Back Voltage VRB 3V66 TDC 3V66 Duty Cycle Spread Disabled 3V66 Period TPERIOD TPERIOD Spread Enabled 3V66 Period 3V66 High Time THIGH 3V66 Low Time TLOW T R / TF 3V66 Rise and Fall Times Any 3V66 to Any 3V66 Clock Skew TSKEW 3V66 Cycle to Cycle Jitter TCCJ PCI/PCIF TDC PCI Duty Cycle Spread Disabled PCIF/PCI Period TPERIOD Spread Enabled PCIF/PCI Period TPERIOD PCIF and PCI high time THIGH PCIF and PCI low time TLOW Condition Min. Max. Unit
Measured at crossing point VOX 45 Measured at crossing point VOX 9.9970 Measured at crossing point VOX 7.4978 Measured at crossing point VOX 4.9985 Measured at crossing point VOX - Measured at crossing point VOX - Measured from VOL = 0.175 to VOH = 0.525V 175 Determined as a fraction of 2*(TR - TF)/(TR + TF) - - - Math averages Figure 11 660 Math averages Figure 11 -150 250 - -0.3 See Figure 11. Measure SE - Measured at crossing point VOX 45 Measured at crossing point VOX 9.9970 Measured at crossing point VOX 4.9985 Measured at crossing point VOX - Measured at crossing point VOX - Measured from VOL = 0.175 to VOH = 0.525V 175 Determined as a fraction of 2*(TR - TF)/(TR + TF) - - - Math averages Figure 11 660 Math averages Figure 11 -150 250 - -0.3 See Figure 11. Measure SE - Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.0V Measurement at 0.8V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.0V Measurement at 0.8V 45 14.9955 14.9955 4.9500 4.5500 0.5 - - 45 29.9910 29.9910 12.0 12.0
55 % 10.003 ns 7.5023 ns 5.0015 ns 100 ps 125 ps 700 ps 20 % 125 ps 125 ps 850 mV - mV 550 mV VHIGH + 0.3 V - V 0.2 V 55 10.003 5.0015 125 300 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 55 15.0045 15.0799 - - 2.0 250 250 55 30.0009 30.1598 - - % ns ns ps ppm ps % ps ps mV mV mV V V V % ns ns ns ns ns ps ps % ns ns ns ns
Rev 1.0, November 22, 2006
Page 13 of 16
CY28409
AC Electrical Specifications (continued)
Parameter Description T R / TF PCIF and PCI rise and fall times Any PCI clock to Any PCI clock Skew TSKEW TCCJ PCIF and PCI Cycle to Cycle Jitter DOT TDC Duty Cycle Period TPERIOD TSKEW Any 48-MHz to 48-MHz Clock Skew USB high time THIGH USB low time TLOW T R / TF Rise and Fall Times Cycle to Cycle Jitter TCCJ USB TDC Duty Cycle Period TPERIOD Any 48-MHz to 48-MHz Clock Skew TSKEW USB high time THIGH USB low time TLOW T R / TF Rise and Fall Times Cycle to Cycle Jitter TCCJ REF TDC REF Duty Cycle TPERIOD REF Period Any REF to REF Clock Skew TSKEW REF Rise and Fall Times T R / TF TCCJ REF Cycle to Cycle Jitter ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up Stopclock Set-up Time TSS TSH Stopclock Hold Time Condition Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured at crossing point VOX Measurement at 2.0V Measurement at 0.8V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured at crossing point VOX Measurement at 2.0V Measurement at 0.8V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured at crossing point VOX Measured between 0.8V and 2.0V Measurement at 1.5V Min. 0.5 - - 45 20.8271 - 8.994 8.794 0.5 - 45 20.8271 - 8.094 7.694 1.0 - 45 69.827 - 0.5 - - 10.0 0 Max. 2.0 500 250 55 20.8396 500 10.486 10.386 1.0 350 55 20.8396 500 10.036 9.836 2.0 350 55 69.855 500 2.0 1000 1.8 - - Unit ns ps ps % ns ps ns ns ns ps % ns ps ns ns ns ps % ns ps ns ps ms ns ns
Table 7. Group Timing Relationship and Tolerances Offset Group 3V66 to PCI Conditions 3V66 Leads PCI Min. 1.5 ns Max. 3.5 ns
Table 8. USB to DOT Phase Offset Parameter DOT Skew USB Skew VCH SKew Typical 0 180 0 Value 0.0 ns 0.0 ns 0.0 ns Tolerance 1000 ps 1000 ps 1000 ps
Table 9. Maximum Lumped Capacitive Output Loads Clock PCI Clocks 3V66 Clocks USB Clock DOT Clock REF Clock Max Load 30 30 20 10 30 Unit pF pF pF pF pF
Rev 1.0, November 22, 2006
Page 14 of 16
CY28409
Test and Measurement Set-up
For Differential CPU and SRC Output Signals The following diagram shows lumped test load configurations for the differential Host Clock Outputs.
CPUT
33 4 9 .9 33 4 9 .9
T PCB
M e a s u re m e n t P o in t
2 pF
CPUC IR E F
475
T PCB
M e a s u re m e n t P o in t
2 pF
Figure 11. 0.7V Load Configuration
O u tp u t u n d e r T e s t P ro b e
Load C ap
3 .3 V s ig n a ls
tD C
-
3 .3 V
2 .0 V
1 .5 V
0 .8 V 0V
Tr
Tf
Figure 12. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement)
Table 10.CPU Clock Current Select Function Board Target Trace/Term Z 50 Ohms Reference R, IREF - VDD (3*RREF) RREF = 475 1%, IREF = 2.32 mA Output Current IOH = 6*IREF Voh @ Z 0.7V @ 50
Ordering Information
Part Number CY28409OC CY28409OCT CY28409ZC CY28409ZCT PB-Free CY28409OXC CY28409OCXT CY28409ZXC CY28409ZXCT 56-pin SSOP 56-pin SSOP - Tape and Reel 56-pin TSSOP 56-pin TSSOP - Tape and Reel Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C 56-pin SSOP 56-pin SSOP - Tape and Reel 56-pin TSSOP 56-pin TSSOP - Tape and Reel Package Type Product Flow Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C
Rev 1.0, November 22, 2006
Page 15 of 16
CY28409
Package Drawings and Dimensions
56-lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
0.249[0.009]
28 1
DIMENSIONS IN MM[INCHES] MIN. MAX.
7.950[0.313] 8.255[0.325] 5.994[0.236] 6.198[0.244]
REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG.
29
56
13.894[0.547] 14.097[0.555]
1.100[0.043] MAX.
GAUGE PLANE 0.25[0.010]
0.20[0.008]
0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.051[0.002] 0.152[0.006] SEATING PLANE 0-8
0.508[0.020] 0.762[0.030] 0.100[0.003] 0.200[0.008]
0.170[0.006] 0.279[0.011]
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 22, 2006
Page 16 of 16

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